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[ The PC Guide | Articles and Editorials | Choosing Your SDRAM ]

How SDRAM Differs from Asynchronous DRAM

Each of the timing operations required to do either a read or write of memory requires a specific amount of time to complete. The next operation cannot begin until the previous one has finished, which means that there is a built-in latency period that must pass before the first piece of data is actually available on the bus. For all current DRAM chips, this latency period is somewhere between 40 and 60 nanoseconds (ns)--this includes SDRAM. The difference between SDRAM and conventional asynchronous DRAM technologies such as FPM or EDO is in how subsequent read operations (after the first one) are handled.

With FPM, only the /CAS line is "cycled" for each subsequent access, to point to the data that is desired next (which may or may not be immediately adjacent to the previous cell). However, the data can only be transferred while the /CAS line is activated. EDO has the same operation as FPM except when the /CAS line is cycled, the data on the output line can still be transferred until the next column access is complete. This allows the data transfer and CAS cycles to overlap somewhat. The net effect is that each of the cycles can be "shortened" somewhat and still allow the same amount of time to actually transfer the data. This is why EDO is slightly faster than FPM, but is at its core fundamentally the same technology.

SDRAM differs from FPM and EDO in several ways. First, SDRAM contains two banks of memory internally instead of one. This allows the second bank to be "precharging" (RAS and CAS activation) while the first bank is transferring data, and vice versa. Essentially, this eliminates the latency for all accesses after the first one. In addition, SDRAM has a "burst mode" capability, which allows it to transfer multiple cells without cycling the /CAS line. This operation is what makes SDRAM "faster" than either FPM or EDO, even though the actual internal operations are essentially the same.

Next: Understanding SDRAM Timing Specifications

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