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Understanding SDRAM Timing Specifications
Now that we understand something about the internal operation of the chips, we need to correlate it with some of the "external timings" that are frequently thrown around by marketing and sales people. As mentioned, each of the operations takes a finite amount of time to complete. Each of these operations also has a "timing symbol" associated with it. We will focus upon those relevant to SDRAM, since there are some additional operations that EDO and FPM don't have (such as bank switching). These symbols are always written like "tCAC", which in this case would mean the Column Access time, and specifies the minimum number of nanoseconds necessary for the operation to complete.
The first important timing symbol to consider is tCLK, which is the system clock speed. If your CPU is running at 233 MHz (3.5x66MHz), then your system clock is running at 66 million cycles per second. This equates to about 15 ns for tCLK. (The clock cycle length in nanoseconds is calculated simply by taking the reciprocal of the clock speed; 1 divided by 66.6 million cycles per seond = 15 x 10-9 seconds per cycle, or 15 nanoseconds per clock cycle). In other words, each clock cycle takes 15 ns to complete. The term "Synchronous" in SDRAM means that every operation in the chip happens in sync with the system clock; therefore any operation that takes 15 ns or less to complete can occur every clock cycle (at 66MHz), but any operation that takes between 16ns and 30ns requires two clock cycles. Note that a 100MHz system clock speed, such as that found on the latest systems running at 350+ MHz, is equivalent to a 10ns clock cycle. This of course means that in order for the SDRAM to complete its activities within one clock cycle, at 100 MHz, everything must happen much faster than it does at 66 MHz.
Now let's look at the timings of the memory itself. For SDRAM, there are 5 important timings:
Each timing factor will play a role in determining the overall performance in any system. Of the five, two are most commonly referenced in marketing and sales literature: read cycle time and tCAC, though you will rarely, if ever, see them called that. Another important timing is the "access time" or tAC.
It's important to note that when you see an SDRAM chip referred to as either "10 ns" or "8 ns", what is really being measured is the "read cycle time". Note that this is not measuring the same timing that EDO or FPM was when they were specified as 60 ns or 70 ns. For the older (asynchronous) DRAM, the timings given were the total amount of time required for a complete memory access (row access, column access and output). In the case of SDRAM, it is the amount of time required to perform a read operation after the initial read (burst mode) that is being given. See this page for more.
The reason this issue of the speed rating is important, is that the PC100 SDRAM spec requires a maximum of 8ns burst cycle time. This does not mean that a chip marked as 10ns will not actually operate at 8 ns (just as a 60 ns EDO chip may actually operate at 50 ns or faster); it just means that there is no guarantee it will operate faster than 10ns in burst mode, which may not be sufficient for use in a 100 MHz system.
Access time (tAC) is the amount of time it takes to "open" the output line from the prior clock "tick". A control line triggers action by a change in state, which is called a "rising edge" (transition from "0" to "1") or "falling edge" (transition from "1" to "0"). When the line "drops", an operation is signaled to begin; however, there is a period of time that must pass before the signal stabilizes. In order to be able to send data out every 10 ns, this time between the last system clock "tick" (rising edge) and the beginning of the output signal must be fast enough to allow the signal to stabilize before beginning the actual output operation. For the PC100 spec, this time is specified as 6 ns.
Another common marketing term attached to SDRAM modules is either "CAS2" or "CAS3". Unfortunately, this is a misnomer; these should be called CL2 or CL3, since they refer to CAS Latency timings (2 clocks vs. 3 clocks). The CAS Latency of a chip is determined by the column access time (tCAC). This is the time it takes to transfer the data to the output buffers from the time the /CAS line is activated.
The "rule" for determining CAS Latency timing is based on this equation:
In English: "CAS Latency times the system clock cycle length must be greater than or equal to the column access time". In other words, if tCLK is 10ns (100 MHz system clock) and tCAC is 20ns, the CL can be 2. But if tCAC is 25ns, then CL must be 3. The SDRAM spec only allows for CAS Latency values of 1, 2 or 3.
OK, now let's put this all together: first the CPU activates the row and bank via the /RAS line. After a period of time (tRCD), the /CAS line is activated. When the amount of time required for column access (tCAC) has passed, the data appears on the output line and can be transferred on the next clock cycle. The time that has passed is approximately 50 ns for the first piece of data to become available. Subsequent transfers may be performed via burst mode (every clock cycle), or by cycling /CAS if necessary (which requires an amount of time dictated by tCAC, also called the CAS Latency period). For burst mode operation, the access time (tAC) must be 6ns, so that the signal can stabilize and an output operation can begin by 8 ns after the last one. The transfer of the data takes 2 ns or less, which means that the data is available every 10 ns on a burst transfer--just in time for the next 100 MHz clock signal!
Next: From Theory to Practice