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Architecture and Operation | Internal Processor Interfaces and
Operation | Instruction Execution Process ]
Native Execution Steps
Native execution processors are those that run standard x86 code directly, without
translation to RISC-like micro-instructions. The actual stages used in execution vary by
the individual processor, with some more advanced ones using more, smaller steps than
others. However, they basically follow the same general path through the processor. These
are the main steps followed; note that they are normally pipelined in a modern CPU:
- Fetch: The first step is to load the instruction into the execution unit so it
can be executed. Since memory is so slow compared to the processor, this stage doesn't
involve a direct read from memory. Rather, special control circuitry loads larger blocks
(16 or 32 bytes) of instruction data from memory and into the primary instruction cache.
This data is then available for rapid feeding to the execution units as needed. Some
processors have prefetch units that do this.
- Decode: The decode stage is used to examine the instruction loaded and determine
how large it is, whether or not it requires an access to memory to read data for
execution, etc. Some processors employ multiple decoders to increase performance.
- Address Generate: Some instructions operate on memory locations while others do
not. For those that access memory, the address of the location is generated in this stage
based on information given as part of the instruction.
- Execute: The instruction is actually executed here, based on information
processed from the earlier steps.
- Write-Back: After the instruction is executed, it produces some sort of a result.
In this stage, the results is written back either to an internal register or the system
memory. Again, system memory is very slow so the result isn't really written to it
directly but rather to a write buffer, where it is held until it can be written to
system memory or the cache.
Note: Don't confuse this
term with write-back as it refers to cache; they are similar concepts but refer to
Next: x86 Translation Execution Steps
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