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DRAM R/W Leadoff Timing
This parameter controls how many clock cycles are required for the first access to memory during a four-read "burst". In modern PCs, reads from the system memory are done in sets of four, because the level 2 cache used in the PC (which is filled by information from the main memory) is 256 bits wide (four sets of 64 bits). The timing, in clock cycles, to perform this quadruple read is normally stated as "x-y-y-y". The first read is slower because the address for the read must be supplied to the memory; the next three are faster because they are read consecutively from the first location (no need to supply an address). Memory system timing is discussed in much more detail here.
Using the x-y-y-y notation, the Leadoff Timing setting refers to the "x" value, the number of clock cycles for the first read. On most BIOSes, this parameter is absolute, and refers to the actual number of clock cycles used for the first access. On others, this setting is the number of additional cycles required for the first access. For example, let's suppose the optimal burst timing for your system is 5-2-2-2. This means the first read takes 5 clock cycles, and the next three take 2 each. In most BIOSes, Leadoff Timing would here be set to 5. In some BIOSes, you would have a parameter called "Leadoff Wait States" or "Additional Leadoff Cycles", and you would put here 3 (the number of additional cycles required for the first read.)
The lower this setting, the faster your system will work. How low you can set this depends on your memory bus speed and the speed and type of memory you are using. In general, the faster your memory bus runs the more cycles it will take to access the memory unless the memory is also made faster. Putting this setting too low will cause memory errors; some of these can appear intermittently and be very difficult to diagnose. Using automatic timing to set this parameter is usually recommended.
By default most BIOSes enable automatic timing settings so this parameter would be "locked out" and not changeable; if you enable manual timing settings this setting will usually default to the slowest possible setting at first, for compatibility reasons.
Note: This setting
controls the timing for both reads and writes. Some systems could have two different
settings instead, one for read leadoff timing and the other for write leadoff timing.
Note: This setting is
normally controlled by the DRAM Timing or Auto Configuration mode, and if automatic
settings are enabled you may not be able to change this.