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When enabled, inserts an extra clock cycle (wait state) between consecutive DRAM read cycles (i.e., consecutive 4-read bursts). Normally the system can perform back-to-back burst reads without this extra delay, and the default for this setting is "Disabled".
Note: This setting is
normally controlled by the DRAM Timing or Auto Configuration mode, and if automatic
settings are enabled you may not be able to change this.
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