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Structure of the Data Store
Many people think of the cache as being organized as a large sequence of bytes (8 bits each). In fact, on a modern fifth-generation or later PC, the level 2 cache is organized as a set of long cache lines, each containing 32 bytes (256 bits). This means that each time the cache is written to or read from, a transfer of 32 bytes takes place; there is no way to read or write just 1 byte. This is done mainly for performance reasons. At the very least, you can't have less than 64 bits per line of cache, because the data bus on a Pentium or later PC is 64 bits wide. The data store is 256 bits wide because memory is accessed in four-read bursts, and 4 times 64 is 256.
Let's take the case of a 512 KB cache (data store). If we wanted to mentally envision how this memory is structured, instead of seeing a single long column with 524,288 (512 K) individual rows, we should instead see 32 columns and 16,384 (16 K) rows. Each access to the data store is a line (row), and the cache has 16,384 different addresses.