Learn about the technologies behind the Internet with The TCP/IP Guide!
NOTE: Using robot software to mass-download the site degrades the server and is prohibited. See here for more.
Find The PC Guide helpful? Please consider a donation to The PC Guide Tip Jar. Visa/MC/Paypal accepted.
View over 750 of my fine art photos any time for free at DesktopScenes.com!

[ The PC Guide | Systems and Components Reference Guide | Motherboard and System Devices | System Cache | Function and Operation of the System Cache ]

Structure of the Data Store

Many people think of the cache as being organized as a large sequence of bytes (8 bits each). In fact, on a modern fifth-generation or later PC, the level 2 cache is organized as a set of long cache lines, each containing 32 bytes (256 bits). This means that each time the cache is written to or read from, a transfer of 32 bytes takes place; there is no way to read or write just 1 byte. This is done mainly for performance reasons. At the very least, you can't have less than 64 bits per line of cache, because the data bus on a Pentium or later PC is 64 bits wide. The data store is 256 bits wide because memory is accessed in four-read bursts, and 4 times 64 is 256.

Let's take the case of a 512 KB cache (data store). If we wanted to mentally envision how this memory is structured, instead of seeing a single long column with 524,288 (512 K) individual rows, we should instead see 32 columns and 16,384 (16 K) rows. Each access to the data store is a line (row), and the cache has 16,384 different addresses.

Next: Cache Mapping and Associativity


Home  -  Search  -  Topics  -  Up

The PC Guide (http://www.PCGuide.com)
Site Version: 2.2.0 - Version Date: April 17, 2001
Copyright 1997-2004 Charles M. Kozierok. All Rights Reserved.

Not responsible for any loss resulting from the use of this site.
Please read the Site Guide before using this material.
Custom Search