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[ The PC Guide | Systems and Components Reference Guide | System Memory | Memory Errors, Detection and Correction ]

Parity Checking

Parity checking is a rudimentary method of detecting simple, single-bit errors in a memory system. It in fact has been present in PCs since the original IBM PC in 1981, and until the early 1990s was used in every PC sold on the market. It requires the use of parity memory, which provides an extra bit for every byte stored. This extra bit is used to store information to allow error detection. Parity checking on newer systems normally requires the appropriate BIOS setting to be enabled. ECC-only modules cannot be used in straight parity-checking mode.

Warning: Don't assume that ordering a new computer system with parity memory means that parity checking will be turned on for you by the technicians who build the PC. Many companies that build PCs take the attitude of "if we leave the BIOS settings on their defaults then we minimize the chances of the PC having a problem". Parity memory is worse than useless if parity checking is disabled! I say "worse" because it fools you into thinking you have protection that you don't really have, which greatly confounds troubleshooting.

Every byte of data that is stored in the system memory contains 8 bits of real data, each one a zero or a one. It is possible to count up the number of zeros or ones in a byte. For example, the byte 10110011 has 3 zeros and 5 ones. The byte 00100100 has 6 zeros and 2 ones. As you can see, some bytes will have an even number of ones, and some will have an odd number.

When parity checking is enabled, each time a byte is written to memory, a logic circuit called a parity generator/checker examines the byte and determines whether the data byte had an even or an odd number of ones. If it had an even number of ones, the ninth (parity) bit is set to a one, otherwise it is set to a zero. The result is that no matter how many ones there were in the original eight data bits, there are an odd number of ones when you look at all nine bits together. This is called odd parity. (It is also possible to have even parity, where the generator makes the sum always come out even, but the standard in PC memory is odd parity). This table shows some examples of how this works:

Sample Data Bits

Number of Ones in Data Bits

Parity Bit

Number of Ones Including Parity Bit

















As you can see, when all nine bits are taken together, there are always an odd number of ones. When the data is read back from memory, the parity circuit this time acts as a checker. It reads back all nine bits and determines again if there are an odd or an even number of ones. If there are an even number of ones, there must have been an error in one of the bits, because when it stored the byte the circuit set the parity bit so that there would always be an odd number of ones. This is how parity memory is used to detect errors--the system knows one bit is wrong, although it doesn't know which one it is. When a parity error is detected, the parity circuit generates what is called a "non-maskable interrupt" or "NMI", which is usually used to instruct the processor to immediately halt. This is done to ensure that the incorrect memory does not end up corrupting anything.

What happens if there is an error in two of the bits? Let's say we have a data byte of 00100100 and this is stored as "00100100 1" including the parity bit. Now let's say this is read back as "01100000 1". Here we have two bits that have flipped, one of them from 1 to 0 and the other from 0 to 1. But the number of ones is still odd! As you can see, parity does not protect against double-bit errors. Fortunately, if the odds of a single-bit memory error are like those of being struck by lightning, the odds of a double-bit error are comparable to those of being struck by lightning twice at the same time. :^)

Incidentally, contrary to popular myth, parity checking does not slow down the operation of the memory system. At all. The parity bit generation and detection is done in parallel with the writing or reading of the system memory, in transistor-to-transistor logic that is much faster than the DRAM memory circuits being used. Nothing in the system ever waits on a "go ahead" signal from the parity checking circuit. It only does anything if it finds an error and when it does, it uses an interrupt.

Next: ECC

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