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Burst Mode Access and Timing
As described in an earlier section, memory is stored as a matrix; to access it you must address it by supplying the row and column that represents what you are trying to read or write. In fact, memory is not read one bit or one byte at a time; usually, it is read 32 or 64 bits at a time (64 on modern PCs).
There are a number of steps that must be taken when performing the initial access to memory that make it relatively slow. There are certain signals that have to be set to begin the access. Then the row address must be sent to the memory, followed by the column address. This tells the memory which cells to use. Then, finally, the data itself is transferred. Because of this overhead, the first access to memory takes a long time--usually from 4 to 7 clock cycles. The amount of time required to perform this first access is called the latency of the memory.
As you can see, most of the overhead is not actually transferring the data itself but telling the memory what and how to do the transfer. If we could somehow lower this overhead, we could greatly increase performance. In particular, what if we read four consecutive 64-bit chunks of memory? In this case, we wouldn't need to supply the address for the second, third and fourth accesses, because they would be consecutive to the first one. This would save a lot of time and improve performance a great deal.
This is exactly what is done in modern computer systems. Four consecutive 64-bit pieces of memory are read one after the other (256 bits or 32 bytes). This is called burst mode access or bursting. The great advantage is that most of the overhead of the first access doesn't have to be repeated for the other three. So instead of those taking 5 to 7 clock cycles, they take only 1 to 3 clock cycles. The system's secondary cache is set to use a width of 256 bits to match this access mode, so it can store all of the 32 bytes read from memory during an access. Modern caches also do this type of burst access.
The timing of burst mode access is generally stated using this type of shorthand: "x-y-y-y". The first number ("x") represents the number of clock cycles to do the first 64-bit read/write. The other numbers are how many clock cycles to do the second, third and fourth reads/writes. An example would be "5-2-2-2", which means 11 clock cycles to do the whole burst. (Without burst mode this access would take at least 20 clock cycles: "5-5-5-5"). It is important to compare memory system timing looking at the amount of time for the full 4-access burst.
Note that all types of memory still have the latency on the first access. This doesn't go away, even with fast memory. Some people for example think that with fast SDRAM you don't need to use secondary cache, because both of them will do a burst transfer in one clock cycle (they both have burst accesses of the form "x-1-1-1"). However, the need to address the memory is still there for the SDRAM and not for the cache. This is why there is still the difference in the first number, the "x": SDRAM is at best 5-1-1-1, while cache is 3-1-1-1 or 2-1-1-1. SDRAM manufacturers confuse things further by only specifying the speed of the module in terms of how fast it will do the burst access--they talk only about the "1", and not the initial "5".