atq111
10-30-2005, 12:45 AM
Dear,
pls let me know the datarate of the DSP processor - TMS320C6711.
its clock speed is 150 MHz,
VLIW is 256 bits wide
register size - 32 bits. has eight 32-bit Instruction per cycle
EMIF is 32bits.
and
The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit
instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by
which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit
of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch
packets are always 256 bits wide; however, the execute packets can vary in size.
:confused:
Pls. asap!
atq
pls let me know the datarate of the DSP processor - TMS320C6711.
its clock speed is 150 MHz,
VLIW is 256 bits wide
register size - 32 bits. has eight 32-bit Instruction per cycle
EMIF is 32bits.
and
The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit
instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by
which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit
of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch
packets are always 256 bits wide; however, the execute packets can vary in size.
:confused:
Pls. asap!
atq