Son of Zeus
10-20-2000, 10:57 AM
The following may be of interest to u; it certainly was to me. Taken from Tom's Hardware coverage of the second day of the 2000 Microprocessor Forum, the full article can be found at: http://www6.tomshardware.com/business/00q4/001011/index.html
“The DRAM maker Micron has discussed in the past its own interests in developing core logic controllers. Micron's Samurai DDR SDRAM chipset was even distributed to several evaluators to serve as a proof of concept project for DDR SDRAM. Although it was rumored that Samurai would eventually reach the market, problems licensing Intel's P6 bus caused Micron to retreat from these ambitions.
Today, however, Micron blew the doors off of a much more powerful core logic controller. This DDR SDRAM chipset, dubbed "Mamba", is designed for the AMD Athlon and leverages design lessons learned from the Samurai. In designing the Samurai, Micron noticed that 40% of its die was unused white space. Wasted silicon translates into wasted money, so Micron searched for a way to more efficiently use the Samurai's die. The Idaho based memory company came up with the idea of embedding an eight megabyte L3 cache into the chipset! Christened "eCache," this L3 cache memory can maintain 9.6 GB/s of sustainable bandwidth. By fabricating eCache on the same die as the memory controller, Micron can reduce latencies by up to 50%!
Obviously such a large, fast cache fabricated intimately with the memory controller can have a profound impact on performance. Micron claims up to a 15% increase in real system performance, which might even be conservative. Micron also asserted that the added cost for the eCache is minimal - "virtually free" are the words Micron's Dean Klein used. An interesting point about this chipset is that the core logic controller is fabricated with a 0.18 micron process while the eCache is implemented at 0.15 microns.
Micron's Mamba might very well turn out to be the standout product of this year's MPF.”
An eight megabyte L3 chipset based "eCache” with 9.6 GBs of sustainable bandwidth at little, or no extra cost gets my vote.
Cast your vote.
Shalom.......Son of Zeus.
“The DRAM maker Micron has discussed in the past its own interests in developing core logic controllers. Micron's Samurai DDR SDRAM chipset was even distributed to several evaluators to serve as a proof of concept project for DDR SDRAM. Although it was rumored that Samurai would eventually reach the market, problems licensing Intel's P6 bus caused Micron to retreat from these ambitions.
Today, however, Micron blew the doors off of a much more powerful core logic controller. This DDR SDRAM chipset, dubbed "Mamba", is designed for the AMD Athlon and leverages design lessons learned from the Samurai. In designing the Samurai, Micron noticed that 40% of its die was unused white space. Wasted silicon translates into wasted money, so Micron searched for a way to more efficiently use the Samurai's die. The Idaho based memory company came up with the idea of embedding an eight megabyte L3 cache into the chipset! Christened "eCache," this L3 cache memory can maintain 9.6 GB/s of sustainable bandwidth. By fabricating eCache on the same die as the memory controller, Micron can reduce latencies by up to 50%!
Obviously such a large, fast cache fabricated intimately with the memory controller can have a profound impact on performance. Micron claims up to a 15% increase in real system performance, which might even be conservative. Micron also asserted that the added cost for the eCache is minimal - "virtually free" are the words Micron's Dean Klein used. An interesting point about this chipset is that the core logic controller is fabricated with a 0.18 micron process while the eCache is implemented at 0.15 microns.
Micron's Mamba might very well turn out to be the standout product of this year's MPF.”
An eight megabyte L3 chipset based "eCache” with 9.6 GBs of sustainable bandwidth at little, or no extra cost gets my vote.
Cast your vote.
Shalom.......Son of Zeus.