Register and cpu question>

[atc_traffic856]

There are two cpus that are from Amd 3400 and the 3500
One is 150nm and the other is 90nm, does this mean the size of the registers?
And if so what are the advantages and disadvantages of the two different sizes? The space within the register contains only one digit regardless of the size, or width of the register. ??
Thank you for your support>

[saphalline]

The nanometer (or micron) size has to do with how small they can make the individual transistors. Well, actually it's an average measure how small the transistors are and how tightly they can pack them. When AMD or Intel says their CPU is based on a 90nm process technology, this means that the average width of a single transistor and the distance to the next transistor is 90nm (90 billionths of a meter). On the chip itself, these sizes and distances aren't always the same, some are more, some are less, but on average it's 90nm.

Being able to squeeze more transistors within a certain area is of great benefit to CPU manufacturers. This lets them not only make smaller chips, but also pack more features into them! More execution units, more transistors dedicated to instruction decoding or branch prediction, and more L2 cache. And since the "process size" is a linear measurement, and since CPU's are made in 2-dimensions, smaller process = much smaller CPU.

For instance, 0.25 microns = 250nm wide (older size used by the original PIII and AMD K6-2). Well, let's put that in 2D form. 250nm x 250nm = 62500 square nm per transistor. Taking the latest example of 90nm, we have 90nm x 90nm = 8100 square nm per transistor. That's a shrinking of almost 8 times!! Taking some more specs, the 0.25 micron PIII had a die size (size of the CPU core itself) of 123 square mm (9.5 million transistors). If Intel were to remake that PIII using the latest 90nm process, the PIII's die size would shrink to a tiny 16 square mm!! :eek: This is the reason that CPU die sizes can get tremendously larger when moving down to a smaller process size. Intel's P4 Prescott actually has a smaller die size than that old PIII, only 112 square mm, but it contains an amazingly large 125 million transistors! That's almost 14 times as many transistors! Pretty cool what they can do, isn't it? :cool:

Obviously since the nm process size is a physical attribute, this doesn't affect the logical attribute of register size. It affects how small the register is on the CPU die :p but not the bit width. Ever get confused by all the numbers? :rolleyes:

Oh, and if you're wondering how the P4 fits 14 times the transistors of the PIII into a die size that's only 8 times smaller, it's because CPU's have more than one layer. They're actually designed a lot like parking ramps - several levels to accomodate all the transistors "parked" in them, with various spots around the CPU that transfer data to different levels. It's actually amazingly complex, and more layers are added as time goes on. The Prescott I believe is up to 7 layers, while the PIII had only 5 (I think, don't quote me on that :p).

[atc_traffic856]

"Wow!" That is really amazing, esp the layering of the Cpu.
I initially thought the numerical numbers refering to the registers were the space that the transistor was held within. But I see as you have explained that the actual number is the size of the tranister, plus the-distance to the next tranister.
Throughout the condensing factor of the Cpus core, and tranisters does the heat build up to a higher state? And inturn this would be the critical area of removing the heat build up, please correct me if I am wrong?
Again you are a wealth of knowledge Saphalline.
Thank you for your time >>

[saphalline]

The shrinking of the transistor lends itself well to lower active power consumption. In other words, the smaller the transistor, the less voltage is required to change its states (from ON to OFF, or vice versa). Less voltage means less power consumption - also, the amperage used inside a CPU is exceedingly small because the transistors and wires connecting them are very tiny and delicate to normal amounts of current. The voltage is also directly related to how fast a transistor changes states. For a P4 Prescott, 1.4V is all that's required to change a transistor's state, whereas the original PIII required 2.0V for its large 250nm wide transistors.

This may not seem all that advanced when looking at just the voltage. It would almost seem like a P4 Prescott would have a voltage 8 times smaller than the original PIII, right? Well not exactly. If the speed were kept the same, the Prescott would indeed probably use a voltage 8 times smaller than the PIII (that would be 0.25V) but because of the core speed increases, the voltage doesn't go down nearly that much. Overall, however, active power consumption has plumetted!

Now you may be asking why is it "active" power consumption? Is there an "inactive" power consumption? Why yes there is! ;) Active power consumption is the amount of power required to change a transistor's state. But transistors have gotten so small that a phenomenon known as electron tunneling has started to wreak havoc within a CPU! Also called current leakage, this is the result of the crazy shrinking. What happens is that a tiny amount of electricity manages to wiggle its way through a transistor when it's not in use. While this tiny amount of electricity isn't enough to change its state or cause any computational errors, it is enough to heat up the transistor and contribute to the CPU's overall power consumption. It's very akin to a leaky faucet that continually drips water even when you try to turn it off - that leaky faucet still uses water and you still have to pay for it when the bill comes! The problem with modern CPU's is that the transistors have gotten so dang tiny that the inactive power consumption is actually greater than the active power consumption!! :eek: The P4 Prescott pumps out an amazingly high 115W of heat at 3.6GHz (on average for the LGA 775 version)! Now imagine that most of that heat is generated by transistors suffering from current leakage. So the poor 3.6GHz Prescott is probably only producing about 30-50W of heat for being used (far less if idle), while the rest is produced from NOT being used!

This impending doom of current leakage is the main reason that current CPU manufacturing tricks are predicted to fail around the year 2010, now just 5 years away! :eek: We are seeing the first signs of major trouble with the Prescott core, and AMD isn't far behind. With AMD's top-end CPU's pushing 2.6GHz, they're just a stone-throw away from suffering major current leakage problems, too! Rumor has it that Intel is throwing in the towel for the NetBurst architecture once Prescott has finished its lifecycle. It may be a lot hotter than Intel expected, but they still shouldn't have any problems pushing past 4GHz and implementing their dual-core plans. After that, though, there just might be a Pentium5 based around an advanced version of the successful mobile core of the PentiumM.

[jlreich]

The problem with modern CPU's is that the transistors have gotten so dang tiny that the inactive power consumption is actually greater than the active power consumption!! :eek:
So you are saying, by using my computer as much as I possibly can, I will actually use less power, and therefor save the earth. :p :D I will have to run that one by my wife. :eek: :D

Great info Saphalline. ;)

[jlreich]

If you don't mind me asking, What is better about the architecture of the Pentium M core that makes it the possible future technology? How do they plan on getting past the problem of current leakage?

[saphalline]

So you are saying, by using my computer as much as I possibly can, I will actually use less power, and therefor save the earth. I will have to run that one by my wife.
Uhh... haha, that's not quite how it works. The inactive power consumption will always be there, regardless of how much of the CPU's power you use. So by using the CPU more (ie 100% usage vs idle) you're still increasing its active power consumption and therefore still increasing the heat. Full load heat output of the Prescott LGA775 3.6GHz is about 151W! :eek: So yes, much higher. Even at full load, however, you can see that a major part of the heat is still inactive power consumption. Therein lies the problem with shrinking the process size.

If you don't mind me asking, What is better about the architecture of the Pentium M core that makes it the possible future technology? How do they plan on getting past the problem of current leakage?
Well, recall how pipelines work. Ok ok, this one's gonna be long, so bear with me... :p

The PentiumM's latest core, called Dothan (also at 90nm process size), has a 10-stage pipeline (major power!!). The Prescott has a 31-stage pipeline. Right there you can see that the PentiumM has a major advantage in terms of raw power. Now consider that inactive power consumption is related to clock speed. Electricity is pumped through the CPU's core in cycles; every extra cycle = another cycle of inactive power consumption. Because the Prescott has such a deep pipeline, it takes on average 31 clock cycles for an instruction to be completed, which is 31 stages of current leakage. The PentiumM has only 10 stages of current leakage per completed instruction.

In terms of transistor count, deeper pipelines break the instruction into smaller chunks in order to get them done faster, right? But a deeper pipeline also adds more transistors as overhead in order to get that instruction done. So the 31 stages of the Prescott actually use more transistors total per completed instruction than the 10 stages of the Dothan. The Prescott also devotes tons of transistors to making up for the deep pipeline, like a more robust branch prediction and the incredibly large and powerful ROB. While the increase in clock speed helps quite a bit for predictable code like encoders/decoders, more random code like games and non-optimized software take a bit of a performance hit. With all those extra transistors, inactive power consumption is actually more of an enemy to deeply pipelined architectures than ever before! The problem that no one saw coming, though, was just how quickly and hard it hit the Prescott core as it approached 4GHz. Up to 3.2GHz, the problem was well in hand, but at 3.6Ghz and 3.8GHz the Prescott is getting really hot!

Not so with the comparable PentiumM at 2GHz. It's plugging along quite well with its 10-stage pipeline and massive 2MB of L2 cache! The other thing about the large amount of L2 cache that has gotten interesting is that onboard L2 cache increases the die size of a CPU, which increases the area of the CPU, which helps to spread out the heat produced by the CPU over a larger area and helps with heat dissipation. Add to that the fact that L2 cache is much cooler per square mm than the core of the CPU where all the computation takes place. So the PentiumM has managed its heat very well compared to the Prescott for all these reasons. Plus the PentiumM's design is much closer to AMD's design of slower clock speeds but more power, and AMD is already the top performer in games and FPU-intensive apps. Their K8-based Athlon64 FX-55 simply stomped the Pentium4 Extreme Edition at 3.46GHz with the new 1066MHz FSB! The FX-55 beat out the P4EE in just about every test, and the new P4EE is even more powerful than the 3.8GHz Prescott, so...

Perhaps Intel is finally realizing that their mobile gem is doing better than the Prescott! At 2GHz full speed, the PentiumM just stomps all over the higher-speed Prescotts! The Centrino platform in general is doing quite well, and now gamers have turned to using the PentiumM in their desktop machines! A properly modified Dothan core would be a perfect contendor as the Pentium5, but Intel is trying to figure out how to market it. Afterall, a PentiumM at 3GHz is going to have major power! But how do you explain that to people who by that time will be used to having 4GHz Prescotts? How will Intel tell them that clock speed no longer matters after having drilled that mantra into mainstream users for all these years? Only time will tell, but there's no denying that Prescott either needs an even smaller process size, or else Intel will be forced to dump its vaunted NetBurst microarchitecture for a more sane design.

[pave_spectre]

But how do you explain that to people who by that time will be used to having 4GHz Prescotts? How will Intel tell them that clock speed no longer matters

Wasn't there some rumour floating around about Intel introducing performance ratings, similar to the AMD system?

[saphalline]

Well that's true. They already have that going with all their CPU's now, so maybe that was just preparation on their part? I still meet many many people who are totally confused by all the numbers, but by keeping their performance ratings, they might just be able to cover their @$$es.

[atc_traffic856]

Thank you for the support and knowledge it is interresting as I can see now why there may be application problems or needless to say that they might stall a bit or even crash, depending on the total amount of applications running and usage at any given amount of time>

[jlreich]

Just so you know, that first post was a joke. I'm always looking for a good excuse to be on the computer. :D :D

So in a nutshell, it sounds like a bigger cache, less pipelines to increase performance. Because bigger cache means better branch prediction, less pipelines mean less of a performance hit if something does go wrong. At the same time, the cache runs cooler than pipelines, therefor lowering temps, along with the help of an inherently bigger die, allowing better heat dissipation. Perhaps this is where water cooling will come in big in the future.

Now if all that is true, you can still only go so far with reducing pipelines, because they are important to performance, allowing more instruction to be executed at one time. My first thought is to increase the size of the die. But that's not practical, as everything keeps getting smaller and smaller. And that would only put a band aid on the real problem, transistors.

Thinking back to our discussion on pipelines(yes Jiggy, pipelines :D ), you said "clock speed cures all". But we are limited in clock speed because of transistor failure, caused by current leakage. So it seems to me, transistors are the real problem. Once we are able to make transistors more efficient, less or no current leakage, then we will truly step up to the next generation of processors.

Assuming my logic is correct, that leaves me with a few questions. It is well known that AMD runs hotter than Pentium. So how are they dealing with the heat problems? Just bigger, better cooling? If I remember correctly, AMD has a bigger die than Pentium, is that because they are using 13 micron instruction, or is that done purposely to help with heat dissipation? Also, why does AMD run so hot, even though they run at lower clock speeds, at the same time out performing Pentium?

Sorry for so many questions. I actually have more, but enough is enough. :rolleyes: :p :D

Thanks for your time Saphalline.

[atc_traffic856]

Would a dual processor rectify alot of the current leakage and also eliminate heat better than a single sys?
You would think that this would be the next step to satisfy the inevitable expansion of software and hardware applications?
I wonder if it would be advantageous to install a dual sys. cpu, already it will assist in pipelining and smt of the pipelining??

Thank you, and also sorry to keep asking all these questions>

[saphalline]

Perhaps this is where water cooling will come in big in the future.
Funny you should say that. Intel is currently looking into to using water-based cooling as the standard stock cooling for their future dual-core CPU's. Probably just a liquid-filled heatpipe design to keep things simple, but I don't doubt that the big OEM's will resort to cooling hoods with venting out the back specifically for the CPU. And OEM's will also be the first to move over to BTX, so that should help even more (ATX is designed attrociously for cooling the latest CPU's).

Yes, everything Intel and AMD do from this point on will essentially be "band-aids". We're going to be able to make it to 2010 using our current Silicon-Germanium method of producing IC's and CPU's, but it's going to require a lot of innovation and sly tricks at the fabs! Already, Intel and AMD have benefited tremendously from SOI (Silicon-on-insulator) and strained-Silicon, which are a couple of tricks that IBM came up with. I don't think Prescott would have been practically possible without those two, and AMD's latest 90nm K8 CPU's are also using these. Transistors are where the problem lies, but again we still have another 5 years of life left, so it's not like we need to solve the problem right now! It's just that it's coming and we need to be prepared. Still too early to see what's coming next, but I'll keep you informed. :D

Yes, AMD has traditionally run about 5-10W hotter than a comparable Intel CPU, especially at idle (for reasons that are still unclear to me). But the fastest Prescotts took a huge leap in heat and literally jumped waaay over what AMD is offering now. This is the part no one saw coming! The 3.2GHz Prescott runs at about 101W at full load (100% CPU usage) but the 3.4/3.6GHz versions run at about 151W!! :eek: What happened?? No one outside of Intel knows for sure, but the 50% increase in heat is truly alarming! It doesn't make sense because the ratio of heat/clock speed skyrocketed just because of 200MHz. 200MHz, that's it! That's nothing to a 31-stage design like Prescott, so everyone in the industry is just scratching their heads at that one.

So while Intel is having major heat issues with Prescott (which is supposed to be cooler since they moved to a smaller process size and increased the L2 cache) AMD is sitting pretty with their 90nm Athlon64's. Moving down to the 90nm size for their Winchester cores reduced heat like normal, so now AMD is looking even better! They are having heat reductions that are on par with expectations (just like every process size shrink should be). The fact that AMD managed to run cooler and Intel now runs hotter, and the fact that they are both using very similar 90nm processes, well... you can see why everyone's confused!

I think the main reason AMD has historically run hotter than Intel is because of their design. Shorter pipeline depth, more execution units, and more layers to their CPU (which doesn't help heat dissipation) all add up to more heat. Also, because AMD CPU's typically hit higher average IPC rates, this means a more efficient design and on average a CPU that does work more often. To wit, AMD's K8 core has 9 layers, while Prescott only has 7.

Would a dual processor rectify alot of the current leakage and also eliminate heat better than a single sys?
You would think that this would be the next step to satisfy the inevitable expansion of software and hardware applications?
I wonder if it would be advantageous to install a dual sys. cpu, already it will assist in pipelining and smt of the pipelining??
I'm still not sure how the upcoming dual-core CPU's will affect heat production within the die. I haven't yet seen any die maps/pics so I can't say for sure. What I imagine is that a dual-core design will create more heat overall, but how exactly the die size will be affected I don't know. It could be that the die size will increase thus making for more heat dissipation per square mm, or it could go the other way. Also, Intel and AMD will undoubtedly have different implementations. The current leakage will always be a problem, and I don't think any amount of designing will make that go away, but transistor placement optimizations could reduce the level of inactive power consumption overall.

The dual-cores will increase overall computing speed by a lot, probably around 70% on average vs a single-core CPU. Of course, we will need software that can take advantage of this! SMT-capable software is a requirement, but WinXP Pro by default can already take advantage of two CPU cores, so that should help. You're all running WinXP Pro, right? :p

The biggest beneficiary to a dual-core design will be the P4 during FPU executions. While the P4 has a powerful FPU alone, it's tied too closely to the two double-pumped ALU's and so are not entirely their own execution units. As a CPU guru would tell you, FXCH is not free on the P4!! :eek: :D This is a big performance-killer for games on the NetBurst microarchitecture, so the dual-core thing should cure this. The other thing to consider is Intel's Hyper-Threading. HT-enabled software runs quite a bit better on the P4 than normal software, so it will be interesting to see exactly how HT and dual-core will work together in a P4. Details are slim so I'm sure about this yet, but I'm keeping my ear to the ground!

AMD's more efficient design will probably make better use of dual-core in terms of keeping all the execution units working as much as possible. AMD also has a much less steeper climb than Intel in the dual-core area. They don't have to worry about shocking heat increases, they don't have to worry about accomodating HT, and their design doens't have a really deep pipeline. Things are going to be quite easy for AMD! Sure they have that onboard memory controller thing, but the RAM bandwidth will probably be shared between the two cores, so this is the only "trick" they have to pull out of their hat. In essence, I would think the onboard memory controller would be easy to reconfigure and also greatly reduces the work load of AMD's chipset partners (the mobo's themselves may only require a BIOS update to work with the upcoming dual-core CPU's!).

Intel had dual-core in mind for quite some time, so the 900 series chipsets are already mostly dual-core ready (as well as EM64T ready). A simple BIOS update for those are also expected (perhaps a few growing pains but overall few should need to buy a new mobo), but the others like VIA and SiS weren't exactly kept in confidence, so their current LGA775 chipsets are not dual-core ready!