CPU data transfer rate

[Russe11]

Hi,

I am studying computer architecture at college and one of my prof's questions appears no-where in our textbook/handouts..

Basically, I need to know the formula to calculate the data transfer rate of a cpu.

Actual question below:

Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-Mhz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate that this microprocessor can sustain?

I would prefer that I wasn't spoon fed the answer.... but rather a detailed description of the necessary calculation...

Thanks,

Russe11

[saphalline]

Welcome to the PC Guide Forums!! :D

This is a common bandwidth question, but with a twist: "a bus cycle whose minimum duration equals four input clock cycles". This is fun! :D

Ok, the fact that this microprocessor is 32-bit is totally unnecessary info for this question - likely just thrown in to complete the story. The info we really need is the external bus width (16-bit), the CPU clock speed (8MHz), and the fact that the external bus clock cycle is 1/4 the speed of the CPU.

So the bandwidth of the external bus (often called the FSB or Front-Side Bus in today's CPU's) is the width times the speed. The width is 16-bit, the speed is 1/4 of 8MHz = 2MHz. So if the external bus can push 16 bits at a time at a speed of 2MHz, how many bits per second is that?

I won't spoon-feed you the answer, as requested, but I can tell you if you get the correct answer. ;)

[Russe11]

Thanks for the warm welcome... :cool:

Ok.... I am starting to understand... however the speed @ 2Mhz ...would that be by the second?
So would it be like 2 to the power of 16?... 64K?

Sorry....getting confused..

Thanks for taking the timw btw in assisting my brain....

Russe11

[Fruss Tray Ted]

2mhz = 2 million or mega - hertz

hertz = cycles per second

16 bits on each cycle

That help any? :p

[saphalline]

Ok, you don't understand speed, either? Let's start at the beginning then.

The unit in question is Hz = Hertz, pronounced "hurts". A Hz is a strange SI unit in that it measures the inverse of another SI unit: the second. So a Hz is an inverse second, mostly referred to as a cycle per second. The Hz unit is commonly used to describe electromagnetic waves and the phenoma they produce.

In a computer system, this phenoma of cycles per second is what drives the clock of the whole system, and all devices base their idea of "time" around this central clock. The CPU in particular needs a clock to determine how often it should do things. Like the one in your question. Let's look at exactly what "time" is to a computer.

The CPU in your question operates at 8MHz. That means it breaks down time into little units per second. The number of units per second in this case is 8 million (1 MHz = 1 million Hz). The CPU sees "time" as being 8 million units per second, with each unit being a clock cycle. Each clock cycle, the CPU does something. The CPU's actions can be one or several clock cycles, but it must be whole clock cycles. In other words, the CPU cannot take 2.4 clock cycles to do something. If it can't do something in 2 clock cycles, it must take 3. Also, the CPU cannot do anything in less than 1 clock cycle, each action must take at least 1 clock cycle. This is the basis for how things get done inside a CPU, and also extends to other devices and even the busses.

A "bus" in a computer is nothing but a collection of traces or wires that connects two devices. Just like everything in a computer, a bus must operate on a clock. Every clock cycle, the bus has an opportunity to transmit data. If no data is ready, no data is sent on that clock cycle. If data is ready just after a clock cycle has past, the bus must wait for the next clock cycle to send that data. Once again, there is no partial clock cycle, only whole ones. Or at least, I won't introduce that idea yet. ;) The amount of data that can be sent by a bus per clock cycle is the bus width - in this case 16-bit. So, each clock cycle, 16 bits of data are sent, or received, depending. Busses go in both directions so it's not a one-way trip. However, when talking about a bus' bandwidth, we are only concerned with how much data can go through the bus per second - we don't care in what direction it goes.

So, is that enough to answer the question now?

[Jiggy]

Hi saphalline,

I read and understood all of that, easy to follow and take in, very informative, thanks.

[Russe11]

saphalline,

I think it has actually sunk in this time...

So if I understood correctly, my problem relates to the following:

16-bit bus * 2 Mhz (2,000,000)
= 32,000,000 bits
= 4,000,000 bytes
= 3906.25 Kb
= 3.814Mb/s

Is that the correct answer?

THANKYOU

[saphalline]

Yep, that's the correct answer! Except... I know, I know, more stuff coming!

When talking about stored data, computer people use the binary system. RAM comes in amounts of binary bytes, like 128MB or 512MB or whatever. And hard drives are converted into binary bytes, like 120GB is really only 111.75GB when you install it.

However, when talking about transmitted data, or data that is going somewhere, computer people use the normal base 10 system. Ie, a 56Kbps modem is 56,000 bits per second in speed, not really 57,344 bits like we normally think of "kilo". Busses are the same way. So in this case, the bus transfer speed would be 4MB/s even, not the actual binary 3.814Mb/s.

Maybe this matters to your prof and maybe it doesn't. I think as long as you list out your calculations on paper the way you just did here, you'll be fine.

[Russe11]

saphalline,

Yep, you have totally cleared the cob-webs from my head on the total issue..
You are extremely knowledgable on the subject of pc architecture...

I always prefer trying to figure out the questions myself until I become completely stuck in the ground...

Thanks for giving me the shovel..

R

[Russe11]

saphalline,

Could you check my answers to these questions please?

Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16-bits wide) and having a 16-bit data bus.

What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?

2^20 = 1048576 bytes / 1024 bytes = 1024 KB = 1 MB (8086 CPU)

What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?

2^16 = 65536 bytes / 1024 bytes = 64 KB (8080 CPU)

I'm hoping that you will say I'm correct... :)

If not :(, Could you explain where I made my mistake?

Thanks for all your assitance and knowledge...

R

[saphalline]

Nope, not quite. You are assuming that this "hypothetical" CPU is a real CPU, but it's not! You have to take those numbers for what they are - 16-bit and 8-bit - not for what actual CPU's have done.

In 16-bit mode, we have 2 ^ 16 = 64KB. In 8-bit mode, we have 2 ^ 8 = 256 bytes.

Now we see exactly how different parts of a CPU can have different bit widths. The part we're calculating here is the address bus width, which determines how much external memory is directly cacheable by the CPU (without any other help). This is in stark contrast to the data bus width which determines how much data per clock cycle can go into or out of the CPU. The address bus width and the data bus width have often been different!

For instance, Intel's first microprocessor (indeed, the FIRST microprocessor) was the 4-bit i4004, which as you probably know has quite the humerous history! :p Anyway, despite the fact that this first CPU could only crunch 4-bits at a time, and had a data bus of 4-bits, it had an address bus of 12-bits - allowing it to cache 4KB of memory. More than enough for a 200KHz calculator microprocessor! Later, as the data bus and internal calculation widths increased, so too did the address bus, often exceeding the widths of the others. Like in your calculations based on the i8080 (8-bit CPU, 16-bit address bus width) and the i8086 (16-bit CPU, 20-bit address bus width). Or how about the odd i8088, which was capable of 16-bit internal calculations, had an 8-bit data bus, and a 20-bit address bus! All modern CPU's have a 36-bit address bus width, giving them a cacheable memory address space of 64GB! :eek: Oh, to be able to have that much RAM...

More interesting things about modern x86 CPU's - the built-in FPU is 80-bits wide, SSE1/2/3 units are 128-bits wide, virtual address space is only 32-bit = 4GB, logical address space is augmented by an onboard MMU (handles page flipping for more memory address space) for a total of just under 64TB, and AMD's K8 core has a huge 128-bit data bus width. Lots of cool stuff to learn about CPU's...

Oh, and if you ever want to have a debate on branch prediction methods as they relate to modern x86 architectures, just let me know! :cool:

[giggling]

what is the meaning of this line"the microprocessor has a bus cycle whose minimm duration equals four input clock cycles."information provide are there is a 16 bit external data bus and the microprocessor has a 8Mhz input clock.