macky2979
05-16-2005, 07:21 AM
1. Is there any merits or benefits in setting device latencies equally?
e.q. IDE/sound/agp card at 64 clocks
2. Does the pci latency of a device indicate something more than the length in bus usage? Does it signify any bearings as to which devices are given more priority by the bus arbiter?
3. I've read the article "PCI latency timer How-To" (http://www.reric.net/linux/pci_latency.html)
over the Net...and it mentions about having a "total system latency".
Quoted :
"All latency timers should be set low enough that if boards A, B, and C all start doing maximum length transfers, board D will still get the bus before max_latency_clocks has elapsed. So,
A.latency_timer + B.latency_timer + C.latency_timer < D.max_latency_clocks
Of course, the device manufacturer might have included themselves in the calculation, and in that case the requirement would be:
A.latency_timer + B.latency_timer + C.latency_timer + D.latency_timer < D.max_latency_clocks
which is easier to calculate anyway, since A+B+C+D could simply be called system_max_latency. If it's greater than any card's max_latency_clocks, you might have trouble."
I'm trying to evaluate my chosen latency values based on this. I assume that some posters here have read the aforementioned article at some point....and may want to shed some light about this, please do so.
First off, I don't know the scope of the devices to be included in the said formula; I always thought that the devices would only be limited to add-on cards, IDE/USB controller and NIC. However, when using PCI latency tool 2.3, I noticed that the SiS 735 single-chip host and the pci-to-pci bridge are also among the "configurable devices" with more than 0 latency. That got me confused whether they should be included in the system_max_latency formula.
e.q. IDE/sound/agp card at 64 clocks
2. Does the pci latency of a device indicate something more than the length in bus usage? Does it signify any bearings as to which devices are given more priority by the bus arbiter?
3. I've read the article "PCI latency timer How-To" (http://www.reric.net/linux/pci_latency.html)
over the Net...and it mentions about having a "total system latency".
Quoted :
"All latency timers should be set low enough that if boards A, B, and C all start doing maximum length transfers, board D will still get the bus before max_latency_clocks has elapsed. So,
A.latency_timer + B.latency_timer + C.latency_timer < D.max_latency_clocks
Of course, the device manufacturer might have included themselves in the calculation, and in that case the requirement would be:
A.latency_timer + B.latency_timer + C.latency_timer + D.latency_timer < D.max_latency_clocks
which is easier to calculate anyway, since A+B+C+D could simply be called system_max_latency. If it's greater than any card's max_latency_clocks, you might have trouble."
I'm trying to evaluate my chosen latency values based on this. I assume that some posters here have read the aforementioned article at some point....and may want to shed some light about this, please do so.
First off, I don't know the scope of the devices to be included in the said formula; I always thought that the devices would only be limited to add-on cards, IDE/USB controller and NIC. However, when using PCI latency tool 2.3, I noticed that the SiS 735 single-chip host and the pci-to-pci bridge are also among the "configurable devices" with more than 0 latency. That got me confused whether they should be included in the system_max_latency formula.