A+ Bus question

[charlieblue]

In the PCGUIDE Reference on System Bus, you reference the PCI bus as the system bus. The terminology in other reviews differentiate between system bus and expansion bus. My currnet understanding is that the system bus is the one connected to the CPU and that links it with memory, power, control, and controller chipsets that link it to the expansion busses such as PCI. Is this understanding correct? Thank you.
Charlie

[saphalline]

Neither are correct anymore. The idea of a main system bus has been stretched to its limits, and it now largely depends on the type of platform you're talking about.

In a 486 or early Pentium system, the PCI bus was indeed the system bus. They were clocked the same and coupled together. You couldn't adjust one and leave the other alone - they were merged. They both ran at 25-33MHz, and in the case of early Pentium systems the chipset contained two chips from a 486 chipset that combined to provide 2 x 30MHz or 2 x 33MHz to the CPU for the system bus.

Fast forward to a Pentium III system and you get into the realm of partial bus speeds. The FSB may have been 66MHz (for Celerons) or 100MHz or 133MHz. The PCI bus was still tied to the system bus, as was the FSB. So the FSB ran at the same speed as the system bus while the PCI bus got a ratio divider (of 1/2 or 1/3 or 1/4) to bring it back down to 33MHz. Again, all three busses were tied together and inseparable.

A Pentium4/Pentium D system works much like an old classic Pentium-class system in that the FSB, PCI bus, and system bus are all inextricably tied, except now we add data rate multiples. A P4's/PD's FSB clock is the same as the system bus speed, except that data is quad-pumped. Address requests still run at the base speed. The PCI bus in this case is decoupled from the other busses such that it can be locked at a certain frequency per the mobo's "tin can".

On AMD's side, we see the same story as the Pentium through Pentium4 bus architecture until we get to the latest CPU's. AMD's latest microarchitecture is their K8 and they did something odd this time. The Athlon64 CPU core has an onboard memory controller. The CPU talks directly to the memory without chipset interaction. If the hard drive, for instance, wants to put data into RAM, it has to talk to the CPU. This brings about many implications, not the least of which is the idea that a chipset need only contain the storage system I/O hub, more often called the Southbridge. The system speed in this case is directly injected into the CPU such that the rest of the system gets its speed from the CPU. The concept of a central backbone system bus is completely obliterated in the latest AMD systems, and even in a P4/PD system it's not entirely clear.

So if you go poking around in a modern system looking for a "system bus", you might just be looking for a loooong time. If it doesn't exist per se, you can't find it.