antares
02-01-2002, 11:06 AM
Greetings all,
From what I know, DMA was created so that the load resulting from transfer instructions is moved from the processor to the DMA controller in order for the processors to do other work.
My question is that, if the system bus is being used for DMA data transfer, can the processor really do that much work in the meantime, given that instructions/data located outside of the memory has to traverse this same (busy) bus to the memory?
I understand that, for example in processors like the M68k, there're two types of DMA modes: cycle stealing and burst, so DMA transfers are only carried out periodically in small time windows (about 0.4 and 1.2 us for the two modes), allowing the bus to be used during other time. My question has to do with the time during transfer itself, the period which the processor is supposed to be "free" to execute other instructions.
Am I confusing myself? If so, please enlighten my poor soul..
Thanks a lot
antares
From what I know, DMA was created so that the load resulting from transfer instructions is moved from the processor to the DMA controller in order for the processors to do other work.
My question is that, if the system bus is being used for DMA data transfer, can the processor really do that much work in the meantime, given that instructions/data located outside of the memory has to traverse this same (busy) bus to the memory?
I understand that, for example in processors like the M68k, there're two types of DMA modes: cycle stealing and burst, so DMA transfers are only carried out periodically in small time windows (about 0.4 and 1.2 us for the two modes), allowing the bus to be used during other time. My question has to do with the time during transfer itself, the period which the processor is supposed to be "free" to execute other instructions.
Am I confusing myself? If so, please enlighten my poor soul..
Thanks a lot
antares