alexz@zoran.co.il
04-01-2002, 04:49 AM
Hi friends. This is my first posting to the forum.
Well, this is engineering-related issue, I hope I can find here engineers dealing with ATA-3 IDE hardware design or just knowledgable in that field people.
I'm trying to work out the interface between certain chip and another one who is bridge between the ATA and USB 2.0.
The data source is the chip which basically compatable with ATA protocol, however supporting Memory mode only, while regular, I/O IDE mode is not.
There are certain diffeernces in signalling between those modes, and some of them rasied the concerns.
First of all, searching through the ATA-3 standard document (Revision 6)
I cannot figure out even one word mentioning Memory mode (as one of IDE signalling modes), while all the explanations, signals and timing diagrams are dealing with the regular I/O mode. Does that mean that the Memory mode is kind of "non-common" or "side" editions to the ATA-3 (IDE) protocol ?
The second question is about IORDY signal of I/O IDE mode. Basically, this signal is intended to stretch the read/write cycle on the bus should the device require longer timing.
The problem is that me Memory mode which is only supported in our chip,
no IORDY functioanlity is available at all and there is no chance to simulate that in any other way (stretching the cycle upon demand).
Luckily, I remember reading in teh ATA-3 standard that the IORDY functionality is only required in PIO modes starting from 3 and higher, while working in lower modes (PIO 0,1 and 2) this is optional.
My second question is whether saying "optional" they mean I can just leave this signal unconnected (or to pull-up/down him acordingly) ?
Thanks in advance, Alex Z
Well, this is engineering-related issue, I hope I can find here engineers dealing with ATA-3 IDE hardware design or just knowledgable in that field people.
I'm trying to work out the interface between certain chip and another one who is bridge between the ATA and USB 2.0.
The data source is the chip which basically compatable with ATA protocol, however supporting Memory mode only, while regular, I/O IDE mode is not.
There are certain diffeernces in signalling between those modes, and some of them rasied the concerns.
First of all, searching through the ATA-3 standard document (Revision 6)
I cannot figure out even one word mentioning Memory mode (as one of IDE signalling modes), while all the explanations, signals and timing diagrams are dealing with the regular I/O mode. Does that mean that the Memory mode is kind of "non-common" or "side" editions to the ATA-3 (IDE) protocol ?
The second question is about IORDY signal of I/O IDE mode. Basically, this signal is intended to stretch the read/write cycle on the bus should the device require longer timing.
The problem is that me Memory mode which is only supported in our chip,
no IORDY functioanlity is available at all and there is no chance to simulate that in any other way (stretching the cycle upon demand).
Luckily, I remember reading in teh ATA-3 standard that the IORDY functionality is only required in PIO modes starting from 3 and higher, while working in lower modes (PIO 0,1 and 2) this is optional.
My second question is whether saying "optional" they mean I can just leave this signal unconnected (or to pull-up/down him acordingly) ?
Thanks in advance, Alex Z