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SCSI(-3) Parallel Interface - 4 (SPI-4)
The latest revision of SPI will be called the SCSI(-3) Parallel Interface - 4 or SPI-4. It is still in development within T10, and goes by the project name "T10 1365-D". Since it is still in the fairly early stages of development, it is unclear at this time exactly what it will include, beyond one feature.
The one feature that we now know will be included in SPI-4 is yet another doubling of maximum throughput on the SCSI bus. This will be accomplished through the implementation of what is being called Fast-160(DT). Like Fast-80, this transfer mode uses double transition clocking, but increases the speed of the bus from 40 MHz to 80 MHz. This results in a maximum theoretical throughput of 320 MB/s on a wide bus. Like the Fast-80 transfers defined in SPI-3, Fast-160 is only supported on 16-bit buses and requires the use of LVD. The marketing people are calling this Ultra320, and despite SPI-4 only being in a draft form at present, products are being readied for the market using the new Fast-160 timing.
Beyond Fast-160, the crystal ball gets a bit hazy. I have seen mention of something called Intersymbol Interference Compensation (ISI), but can't find any information on it at present. I have also read that the packetization feature introduced in SPI-3 may be required for Fast-160 transfers. All of this information should be considered just rumor until the standard gets closer to being approved. Since new standards often change frequently before being finalized, I will probably wait until the dust settles before updating this page.