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Pipelined Burst (PLB) Cache
Pipelining is a technology commonly used in processors to increase performance; in the pipelined burst (PLB) cache it is used in a similar way. PLB cache adds special circuitry that allows the four data transfers that occur in a "burst" to be done partially at the same time. In essence, the second transfer begins before the first transfer is done, just the way you can start pouring a second gallon of fluid down a pipeline before the first gallon has finished exiting the other side.
Because of the complexity of the circuitry, a bit more time is required initially to set up the "pipeline". For this reason, pipelined burst cache is slightly slower than synchronous burst cache for the initial read, requiring 3 clock cycles instead of 2 for sync burst. However, this parallelism allows PLB cache to burst at a single clock cycle for the remaining 3 transfers even up to very high clock speeds; this means 3-1-1-1 speed up to even 100 MHz bus speeds. PLB cache is now the standard for almost all quality Pentium class motherboards.