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Synchronous Burst Cache
Unlike asynchronous cache, which operates independently of the system clock, synchronous cache is tied to the memory bus clock. Each tick of the system clock, a transfer can be done to or from the cache (if it is ready). This means that it is capable of handling faster system speeds without slowing down the way asynchronous cache does. However, the faster the system runs, the faster the SRAM chips have to be, in order to keep up. Otherwise timing problems (crashes, lockups) occur.
Even this type of cache slows down at very high speeds. It is capable of 2-1-1-1 operation up to 66 MHz, but then it slows down to 3-2-2-2 at higher speeds (which are starting to become more popular and will become even moreso in the future). Synchronous burst cache never quite caught on; pipelined burst cache was developed at around the same time and seemed to take the market away from sync burst before the latter could really get going.