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Double Transition Clocking
As mentioned in the previous page, the speed of the clock on an interface or bus directly controls the performance or throughput of that interface or bus. The one constant in the PC world is the desire for increased performance. This in turn means that most interfaces are, over time, modified to allow for faster clocking, which leads to improved throughput.
Many newer technologies in the PC world have gone a step beyond just running the clock faster. They have also changed the overall signaling method of the interface or bus, so that data transfer occurs not once per clock cycle, but twice. Usually, this is implemented by having data transfer on both the rising and falling edges of the clock, instead of just one or the other. The change allows for double the data throughput for a given clock speed. This technology is called double transition clocking, as well as several other similar names (such as dual-edge clocking, or double-trigger timing, for example.)
Why bother with this change at all, one might ask? Why not just increase the speed of the clock by a factor of two? Of course, that's been done many times already on most interfaces. To whatever extent possible, interface designers do regularly increase the speed of the system clock. However, as clock speeds get very high, problems are introduced on many interfaces. Most of these issues are related to the electrical characteristics of the signals themselves. Interference between signals increases with frequency, and timing becomes more "tight", increasing cost as the interface circuits must be made more precise to deal with the higher speeds.
Double transition clocking was seen as an obvious opportunity to exploit because it allows increased performance without the engineering problems associated with increasing clock speed. Of course, the two are really independent. The use of double transition clocking has not eliminated engineering efforts to increase clock speed as well.
Note: It is also possible for
an interface to be designed to perform more than two data transfers during each clock
cycle. The AGP "4x" mode is so
named because it transfers data four times during each cycle.